Esd Protection Design for Rf Circuits in Cmos Technology with Low-c Implementation
نویسندگان
چکیده
To mitigate the radio-frequency (RF) performance degradation caused by electrostatic discharge (ESD) protection device, low capacitance (low-C) design on ESD protection device is a solution. With the smaller layout area and small parasitic capacitance under the same ESD robustness, silicon-controlled rectifier (SCR) device has been used as an effective on-chip ESD protection device in RF ICs. In this paper, the modified lateral SCR (MLSCR) with the waffle layout structure is studied to minimize the parasitic capacitance and the variation of the parasitic capacitance within ultra-wide band (UWB) frequencies. With the minimized parasitic capacitance, the degradation on RF circuit performance can be reduced. Besides, the fast turn-on design on MLSCR without extra parasitic capacitance from the trigger circuit adding on the I/O pad is also investigated in this work.
منابع مشابه
Co-Design Strategy With Low-C Consideration for On-Chip ESD Protection in RF ICs
Co-design strategy with low-capacitance (low-C) consideration for on-chip ESD protection in RF ICs is a solution to mitigate RF performance degradations caused by ESD protection device. A low-C design on ESD protection device was presented in this paper. An RF power amplifier (PA) codesigned with the low-C ESD protection device was also presented in this paper. Before ESD stress, RF performance...
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